The present invention generally relates to cell switching systems and, more particularly, relates to a cell switching system using an asynchronous transfer mode which is a mode for realizing a broad-band multimedia switching system.
A cell switching system of asynchronous transfer mode (hereinafter referred to as "ATM cell switching system") having such a configuration as disclosed in Japanese Patent Publication JP-A-59-13599 is known. The principle of operation of the ATM cell switching system of the JP-A-59-13599 will be described briefly with reference to FIG. 1. In the following description, each cell (which is also called a "packet") 10 to be switched is assumed to have a fixed length of 35 bytes composed of a 3-byte header 12 and a 32-byte user data portion 11 as shown in FIG. 2. The header 12 includes a logical channel number (hereinafter abbreviated to "LCN") for identifying the logical channel to which the cell belongs. Cell switching is executed by identifying the destination of the cell at every switching node on the basis of the LCN.
The above-mentioned values of the respective byte lengths of the entire cell, the header and the data are determined for convenience' sake of explanation, while those values are not determined on the basis of the basic principle of the present invention.
FIG. 1 shows a basic construction of the conventional ATM cell switching system provided with 32 input lines 201a-201n and 32 output lines 217a-217n. Such a cell 10 as shown in FIG. 2 is periodically applied to each of the 32 inputs 201a to 201n synchronously with each other. The respective input cells are converted from serial data into parallel data by means of a multiplexer circuit 203 so that the respective headers of the input cells are multiplexed and transferred onto a line 204 and the respective user data of the input cells are multiplexed and transferred onto a line 205. The line 204 is used for transferring parallel data of 24 bits (3 bytes) and the line 205 is used for transferring parallel data of 256 bits (32 bytes). The user data is written in an input-line-corresponding buffer memory 206 while the address of the user data is designated by an output line 208 of a counter 207. In this example, the output from the counter 207 is composed of 9 bits in which the upper 5 bits are used for designating any one of the input lines 201a to 201n. The buffer memory 206 has a memory capacity for 16 cells corresponding to each of the input lines. The lower 4 bits of the counter 207 are used for designating the cell address successively. Accordingly, the buffer memory 206 operates to successively store cells 10 periodically applied through the input lines into addresses designated by the counter 207, so that writing of cells in the whole cell area of the buffer memory 206 is perfected in 16 periods. Thereafter, writing of cells is performed periodically so that new cells are successively overwritten in the area where old cells have been written. Accordingly, unless a cell stored in the buffer is read out of the buffer within 16 periods so as to be sent out through a switching system, the old cell will be lost in the switching system because a new cell will be overwritten on the old cell.
On the other hand, the headers 12 of respective cells 10 are fed to a header converter circuit 209 through the line 204. For example, the header converter circuit 209 may be constituted by a memory table. The memory table is read by an address determined by a combination of the LCN contained in the header of a cell and the number of the input line through which the cell is applied, so that routing data of the header, that is to say, an output line number and an LCN (generally, different from the LCN contained in the input header) for identifying the cell on the output line, are fed onto lines 210 and 211, respectively. The output line number on the line 210 is composed of 32 bits which respectively correspond to the output lines. The output line number indicates the fact that the cell will be transmitted to the output lines corresponding to the bit position where the bit takes "1". The LCN appears on the line 211 in synchronism with the writing of the user data of the cell in the input-line-corresponding buffer memory 206, and is written into a cell area of the buffer memory together with the user data.
The address of the buffer memory 206 where the cell has been written is fed to a group of output queues 212a to 212n through the line 208 and is stored in one output queue designated by the output line number. The output queues 212a to 212n correspond to the output lines 217a to 217n, so that the address on the buffer memory 206 for one cell to be outputted is stored in the corresponding one of the output queues for a corresponding one of the output lines. Those output queues 212a to 212n are successively designated by the output of the counter 207 so that the contents of the buffer memory 206 are read out corresponding to the successively designated contents of the output queues, that is, addresses, and outputted to a line 215. Accordingly, cells to be transferred onto the output lines 217a-217n exist on the line 215 in the multiplexed form. Those multiplexed cells are demultiplexed through a demultiplex circuit 216 and then the demultiplexed cells are respectively correspondingly transferred onto the 32 output lines 217a to 217n.
The aforementioned ATM switching system however requires a switching function for broadcast mode. The broadcast mode is a mode in which one cell inputted through an input line is outputted onto a plurality of output lines. In the case of the conventional system as shown in FIG. 1, one and the same address of the buffer memory 206 is written in the plurality of output queues by putting "1" in a plurality of bit positions on the line 210. As a result, one and the same address can be read from the plurality of output queues when the cell is to be outputted, and accordingly, one and the same cell can be transferred onto the plurality of output lines.
In this case, it is a matter of course that the respective broadcast cells have not only one and the same data but also one and the same contents of the header. Accordingly, call control must be carried out on the assumption that the broadcast cells on the respective output lines have one and the same LCN.
The aforementioned conventional switching system has a problem that the quantity of hardware in the memory constituting the address queues 212a-212n becomes large. In particular, when priority, for example, classified by service classes, is established in handling cells in ATM switching, queues must be set as classified by service classes, so that the quantity of hardware is even further increased.
Further, in cell transmission in the broadcast mode, a broadcast cell is stored with one and the same address as the buffer memory 206, in each of the queues through which the broadcast cell is to be transmitted. Accordingly, a problem arises in that the capacity of the queues for storing cells belonging to other LCNs is reduced. For example, in the example shown in FIG. 1, it is a necessary and sufficient condition that the output queues have an address storage capacity for 16 periods, that is, for 16 cells, because the input-line-corresponding buffer memory 206 is always updated or overwritten with the passage of time of 16 periods or more. Accordingly, for example, in the case where 16 broadcast cells to be transmitted onto all the output lines are inputted in one period, all the queues are occupied by those broadcast cells so that other input cells become lost because of lack of vacant queues.
Even if the number of cells inputted in several periods before and after the period in which 16 broadcast cells are inputted is not so large that the total throughput in the switching system for the short duration or the throughput in every output line is within a limit of output throughput, lost cells may occur in case of instantaneous concentration of broadcast cells. This is a serious problem in the traffic performance of the switching system. To solve these problems by the conventional system construction, both the capacity of the queues 212a to 212n and the capacity of the input-line-corresponding buffer memory 206 must be increased. However, a disadvantage arises in that efficiency in use of the memory is lowered, because the increased portion of the buffer memory is not used when there is no concentration of broadcast cells.